1. Field of the Invention
The present invention relates to a semiconductor device, for example, a semiconductor memory device, having a resistance element in the peripheral circuit region and to the process for its fabrication. More particularly, the invention relates to a dynamic random access memory (DRAM) comprising a resistance element in the attached peripheral circuit region therein and an MIM or MIS structure as a cell capacitor therefor and to the process for its fabrication.
2. Description of the Prior Art
Some kinds of semiconductor devices, such as semiconductor memory devices, are composed of a memory circuit part, for example a memory cell part of a DRAM (a dynamic random access memory), which is a main constituent element thereof, and additionally attached peripheral circuit parts. A self-refresh circuit built in the DRAM is an example of the attached peripheral circuits. In the self-refresh circuit, a timer for the circuit of course includes a resistance element. Development and application of a combined installation type semiconductor memory device and a hybrid type semiconductor memory device comprising a logic circuit as an attached circuit in addition to the memory circuit are just in progress. Under such circumstances, it has been required to fabricate elements constituting various kinds of peripheral circuit parts to be formed together with a memory circuit part, which is a main constituent element, on a single substrate in the same process. For example, a resistance element is one of the elements composing those peripheral circuit parts and formed to have a desired resistance value using a conductive material with a relatively high resistivity.
On the other hand, the integration degree of the above-mentioned memory cell part is rised, and accordingly the surface area of a unit cell is considerably reduced. To accomplish the required reduction in the surface area of the unit cell, a dielectric material having a higher dielectric constant tends to be used for a cell capacitor instead of a conventionally used silicon oxide film or silicon nitride film for, for example, a layered structure of oxide/nitride/oxide films. A capacitor with a MIM or MIS structure is employed using, for example, Ta2O5 film or various kinds of oxides with perovskite structure as a capacitor insulation film. A high-dielectric oxide material with the above-mentioned perovskite structure to be used for the capacitor insulation film includes, for example, BST ((BaxSr1-x)TiO3) type materials.
When a silicon oxide film or a silicon nitride film is used as the capacitor insulation film in the configuration of a capacitor with the MIM or MIS structure, a polysilicon layer is commonly used for an upper electrode layer (the M layer). The polysilicon layer to be employed for the upper electrode layer may not be a low resistance layer, and indeed such having a resistivity of about 10xe2x88x923 xcexa9cm is also employed. Further owing to the requirement in terms of functions, the polysilicon layer for the above-mentioned upper electrode layer is evenly deposited on an interlayer insulating film by a vapor phase deposition, so that the layer is used, for example, as a resistance layer of a resistance element to be composed in a peripheral circuit part. In other words, the polysilicon layer deposited on an interlayer insulating film of the peripheral circuit part is patterned in a desired shape to obtain a resistance element with a predetermined resistance value.
In the case an oxide such as BST with the perovskite structure is employed as the capacitor insulation film in the configuration of a capacitor with the MIM or MIS structure an undesired phenomenon such as mutual diffusion of formation of a low dielectric layer on the interface is caused by using polysilicon for an electrode layer. In order to avoid such an undesired phenomenon, configuration is employed where a double layer of, for example, Ti (titanium)/TiN (titanium nitride) is formed as a barrier layer to prevent mutual diffusion, or where Ru (ruthenium), Ir (iridium), or the like or its conductive oxide, e.g. RuO2 (ruthenium oxide), IrO02 (iridium oxide), or the like is used for an electrode layer itself. Platinum-group metals such as Ru and their oxides, which all have excellent conductivity, are suitable for an electrode material with sufficiently low resistivity to increase the integration degree and to decrease the capacitor surface area. Further, a double layer of Ti/TiN to be used for the barrier layer to prevent diffusion is also applicable to an electrode material with sufficiently low resistivity, and, even when such a barrier layer is inserted, increase of the resistance in the direction of the electrode layers (increase of series resistance) is not caused.
On the other hand, in the case the above-mentioned material such as Ru or RuO2, or the barrier layer such as Ti/TiN double layer is employed, the sheet resistance in the in-plane direction (the lateral direction) of the whole electrode layer is remarkably low as compared with that of a conventional polysilicon owing to the considerably low resistivity. For that, in a semiconductor device using a polysilicon layer for a conventional cell capacitor upper electrode, the same polysilicon layer is also used as the resistance layer in a resistance element for composing the peripheral circuit part, however in the case material such as Ru or RuO2 is used for the cell capacitor upper electrode, an element configuration in which the conductive material layer for the upper electrode is used as a resistance layer of a resistance element can no longer be applicable. That is, assuming, as illustrated in FIG. 2, the above-mentioned Ru or RuO2 is used for the resistance layer, there is need to employ means of significantly narrowing the line width of the resistance layer or significantly elongating the whole length of the route of the resistance pattern for increasing the resistance value of the resistance element, however it is difficult to employ such means owing to practical restriction relevant to such as the patterning precision and the element size.
Object of the Invention
Because of the above described reason, in the case material such as Ru or RuO2 is used for the cell capacitor upper electrode, a polysilicon layer having a desired conductivity (resistivity) is required to be separately formed only for the purpose of forming the resistance element and patterned to obtain a predetermined resistance value. It is strongly required to make the element arrangement in the whole semiconductor device practically same as that in a conventional case where a polysilicon layer is used for the cell capacitor upper electrode. In company with that, if a process of composing a resistance element is carried out after a process of patterning Ru or RuO2 of the cell capacitor upper electrode, not only the process takes additional steps but also the polysilicon layer for the resistance element has to be aligned with the patterned upper electrode and patterned at high precision. Increase of the above-mentioned extra patterning steps, especially, a photolithographic step is desirably suppressed, if possible, in the case of highly dense integration and thus an innovative proposal of a semiconductor device structure enabling fabricating a resistance element using a polysilicon layer having a desired conductivity (resistivity) while avoiding the increase of the photolithographic step.
The present invention is to solve the above-mentioned problems and the purposes of the present invention is to provide a semiconductor device structure employing an innovative structure for a plate electrode to be used in a semiconductor device, for example, a semiconductor memory device. For example, in the case of a semiconductor memory device comprising the above-mentioned resistance element composed using a cell capacitor with an MIM or MIS structure wherein a conductive material such as Ru with low resistivity is used for the upper electrode and a conductive material with a high resistance such as polysilicon is used, the purpose is to provide an innovative structure of the semiconductor memory device without practically increased photolithographic steps, compared with the case of fabricating the resistance element using the same conductive material of a conventional cell capacitor upper electrode. More practically, the purpose of the present invention is to provide a new semiconductor memory device structure in which the configuration of the above-mentioned cell capacitor upper electrode and resistance layer of the resistance element and parts in company with them is modified. In addition to that, the present invention has another purpose to provide a process for fabricating the innovative semiconductor memory device configuration, that is, a new fabrication process.
In order to solve the above-mentioned problems, the inventor has tried to re-design the configuration and partial configuration of a cell capacitor upper electrode, a resistance layer of a resistance element and their peripheral parts and to select processing technique applicable for the configuration, and then he has found it possible to carry out patterning without causing unnecessary side etching of a polysilicon layer, which is an uppermost layer and an insulating layer, which is an intermediate layer, at the time when dry etching using etching mask of a photoresist is applied in successive patterning of the three-layer structure in which a polysilicon layer is layered on the insulating layer of such as SiO2 on the layer of a metal or conductive oxide or nitride, e.g. Ru (ruthenium), Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), W (tungsten), WN (tungsten nitride), Pt (platinum), Ir (iridium) and SRO (strontium-ruthenium-oxide) to be used for the cell capacitor upper electrode. Consequently, it is made sure that a resistance element with a desired element surface area and a predetermined resistance value just as same as those of a resistance element comprising a resistance layer of a conventional polysilicon can be obtained using a polysilicon layer formed by patterning the above-mentioned three-layer structure as the resistance layer. Additionally, it is also found that there are proper conditions of dry etching with high anisotropic degree selectively and separately for the interlayer insulating film, the polysilicon layer, and the insulating film layer in the case of forming the interlayer insulating film on the above-mentioned three-layer structure and forming a contact hole for connecting, for example, an aluminum electrode and wiring formed on the interlayer insulating film with a cell capacitor upper electrode Ru or the like under the interlayer insulating film. Based on those findings, the present invention is achieved.
A semiconductor device of the present invention is a semiconductor device comprising a plate electrode as a constituent element, wherein the plate electrode is made to have a three-layer structure of a low resistance conductive material layer, an insulating film layer with a predetermined film thickness formed on the conductive material layer, and a high resistance conductive material layer formed on the insulating film layer, wherein these three layers of the three-layer structure are patterned in the same shape. For example, the high resistance conductive material layer has a sheet resistance of 50 to 1010 xcexa9/xe2x96xa1 and the low resistance conductive material layer has a sheet resistance of 1 to 40 xcexa9/xe2x96xa1. Particularly, the high resistance conductive material layer is a conductive material layer using silicon and the low resistance conductive material layer is preferably a layer containing a low resistance conductive material selected from Ti, TiN, Ta, TaN, W, WN, Ru, Pt, Ir and SRO.
Further, in the semiconductor device of the present invention, the low resistance conductive material layer of said electrode with the three-layer structure is used
In the case the above-mentioned invention is applied, for example, to a semiconductor memory device, the semiconductor memory device comprises a resistance element in the peripheral circuit part and is characterized by being provided with the resistance element and the cell capacitor composed in the manner wherein: the cell capacitor to be employed for the memory cell of the above-mentioned semiconductor memory device has an MIM or MIS structure composed using a low resistance conductive material selected from a low resistance metal, metal nitride or metal oxide for the upper electrode brought into contact with the dielectric film layer; the above-mentioned resistance element comprises a high resistance conductive material layer as a resistance layer; a three-layer structure is composed of the low resistance conductive material layer, an insulating film layer with a predetermined film thickness and formed on the low resistance conductive material layer, and the high resistance conductive material layer formed on the insulating film layer; and the above-mentioned resistance element and cell capacitor is formed as follows, respectively: the above-mentioned resistance element is formed by patterning the above-mentioned three-layer structure into a predetermined shape and employing only the uppermost high resistance conductive material layer as the resistance layer; and the above-mentioned cell capacitor is formed by patterning the above-mentioned three-layer structure into a predetermined shape of which the lowermost layer is as the upper electrode.
It is preferable to use an oxide with a perovskite structure for the above-mentioned dielectric film layer and to select a low resistance conductive material to be used for the upper electrode of the above-mentioned cell capacitor from Ti, TiN, Ta, TaN, W, WN, Ru, Pt, Ir and SRO. Further, it is preferable to select the same material for the insulating film layer to be the intermediate layer of the above-mentioned three-layer structure as a material to be used for the interlayer insulating film and it is more preferable to select, for example, silicon oxide. In addition to that, polysilicon may be used for the high resistance conductive material layer. Generally, a further interlayer insulating film is formed as to coat the above-mentioned cell capacitor and the resistance element.
The process for fabricating the semiconductor memory device of the present invention is characterized in that: the cell capacitor to be employed for the memory cell of the above-mentioned semiconductor memory device is made to have an MIM or MIS structure composed using a low resistance conductive material selected from a low resistance metal, metal nitride or metal oxide for the upper electrode brought into contact with the dielectric film layer and characterized by comprising steps of layering the above-mentioned low resistance conductive material layer on a substrate; layering an insulating film layer with a described film thickness so as to coat the low resistance conductive material layer; layering a high resistance conductive material layer so as to coat the insulating film layer; forming an etching mask containing a predetermined shape of the above-mentioned resistance element and the predetermined shape of the above-mentioned upper electrode on the layers of the three-layer structure by a photo lithographic method; pattering the three-layer structure by dry etching using the etching mask; and after that removing the etching mask.
In general, it is preferable to carry out a step of forming a further interlayer insulating film so as to coat the high resistance conductive material layer of the resistance element formed by the patterning and a high resistance conductive polysilicon layer coating the upper electrode of the cell capacitor in the same shape after the step of removing the etching mask.